request_irq (Kernel)

This call allocates an interrupt and establishes a handler; If this function is executed in guest kernel, it will

What is timer interrupt?

Timer interrupts allow you to perform a task at very specifically timed intervals regardless of what else is going on in your code.

What is architecture-defined exceptions and interrupts?

The allowable range for vector numbers is 0 to 255. Vector numbers in the range 0 through 31 are reserved by the Intel 64 and IA-32 architectures for architecture-defined exceptions and interrupts.

Does there exist any interrupts not architecture-defined?

0-31: #PF, #AC, #MC etc.

32-255: User defined, to external IO devices.

What's the relationship between pin and vector?

Pin is a physical thing on the processor, a pin is not a vector, many vectors can delivered by a pin.

Terminologies

IDT (Interrupt Descriptor Table)

IDTR (Interrupt Descriptor Table Register)

INTR

LVT (Local Vector Table)

IVT (Interrupt-Vector Table)

IRQ (Interrupt Request)

PIC (Programmable Interrupt Controller)

IST (Interrupt Stack Table)

Inter-processor Interrupt (IPI)

Interrupt line

It may denotes the Pin-based IRQ: system call - What's the difference between an interrupt line and the interrupt number - Reverse Engineering Stack Exchange

Interrupt vector

Just a number associate with an exception or interrupt.

Each device is assigned a unique Interrupt Vector Number (Microsoft windows calls it Interrupt Request Number or IRQ).

All interrupts are assigned a number from 0 to 255.

Each entry of the interrupt vector table (IVT), called an interrupt vector, is the address of an interrupt handler.

LDT

The processor uses the vector number as an index into the IDT. The table provides the entry point to an exception or interrupt handler.

INTR

You can think it as a pin.

External interrupts are received through

  • pins on the processor
  • through the local APIC. The primary interrupt pins are the LINT[1:0] pins, which are connected to the local APIC.
  • When the local APIC is enabled, the LINT[1:0] pins can be programmed through the APIC’s local vector table (LVT) to be associated with any of the processor’s exception or interrupt vectors.
  • When the local APIC is global/hardware disabled, these pins are configured as INTR and NMI pins, respectively. Asserting the INTR pin signals the processor that an external interrupt has occurred. The processor reads from the system bus the interrupt vector number provided by an external interrupt controller, such as an 8259A. Asserting the NMI pin signals a non-maskable interrupt (NMI), which is assigned to interrupt vector 2.

IVT

interrupt-vector table

Interrupt

interrupt (sometimes referred to as a trap).

Processors typically have an internal interrupt mask register, Interrupt - Wikipedia which allows selective enablingInterrupt - Wikipedia(and disabling) of hardware interrupts. Each interrupt signal is associated with a bit in the mask register.

Some interrupt signals are not affected by the interrupt mask and therefore cannot be disabled; these are called non-maskable interrupts (NMIs). These indicate high-priority events which cannot be ignored under any circumstances.

The terms interrupt, trap, exception, fault, and abort are used to distinguish types of interrupts, although "there is no clear consensus as the exact meaning of these terms".

Interrupt - Wikipedia

implementations:

  • Intel 8259 PIC
  • Local APIC
  • I/O APIC
  • MSI in PCI /PCIE (Junming's report)

Interrupts type

By interrupter:

  • External (hardware generated) interrupts.
    • Non Maskable Interrupt
      • External hardware asserts the NMI pin
      • The processor receives a message on the system bus or the APIC serial bus with a delivery mode NMI.
    • Maskable Interrupt: Any external interrupt that is delivered to the processor by means of the INTR pin or through the local APIC is called a maskable hardware interrupt.
      • Through INTR pin: 0-255
      • Through the local APIC: 16-255
  • Software-generated interrupts (INT n): Any of the interrupt vectors from 0 to 255 can be used as a parameter in this instruction.
  • Exceptions.

Exception type (trap, fault, abort)

By source:

  • Processor-detected program-error exceptions.
  • Software-generated exceptions.
  • Machine-check exceptions.

By type:

Exceptions are classified as faults, traps, or aborts depending on the way they are reported and whether restart of the instruction that caused the exception is supported.

  • fault: reported "before" the instruction causing the exception.
  • trap: reported at the instruction boundary immediately after the instruction in which the exception was detected.
  • abort: permits neither precise location of the instruction causing the exception nor restart of the program that caused the exception. Aborts are used to report severe errors, such as Machine Check (#MC).

可以在这里看到所有的异常号：SDM 6.3.1 External Interrupts Table 6-1, and section 6.6.

80386 Programmer's Reference Manual -- Section 9.1

Interrupt in Linux

Re-entrency / nested

Q: Can interrupts be nested in Linux?

A: It used to be nested, but now it can't.

Linux的中断可以嵌套吗？ - 知乎

Linux used to support nested interrupts but this was removed some time ago in order to avoid increasingly complex solutions to stack overflows issues.

Interrupts — The Linux Kernel documentation

PIC (8259A)

IRR, IMR, ISR in PIC (8259A)

CPU 上的引脚：INTR, INTA。PIC 上的引脚: INT, INTA。请求是从 PIC 的 INT 到 CPU 上的 INTR，响应是从 CPU 上的 INTA 到 PIC 上的 INTA。

中断由 IR0-IR7 进入，进入之后 PIC 会自动设置 IRR 的对应 bit，经过 IMR 和优先级处理之后，选择优先级最高的中断，通过 INT 管脚发送中断给 CPU，CPU 收到中断后，如果决定处理该中断，就会通过 INTA 管脚向 PIC 发送中断已接收通知，PIC 接到该通知之后，设置 ISR，表明某中断正在由 CPU 处理。清空 IRR，表示这个请求已经接收到了。

当 CPU 处理完该中断之后，会向 PIC 发送 EOI (end of interrupt) 信号，PIC 收到 EOI 后，会将 ISR 中对应的 bit 清除掉。PIC 记录 ISR 的作用之一是当后续收到新的中断时，会将新的中断和正在处理的中断的优先级进行比较，进而决定是否打断 CPU 正在处理的中断。如果 PIC 处于 AEOI (auto EOI) 模式，CPU 无需向 PIC 发送 EOI 信号。

  • IRR: Interrupt Request Register
  • ISR: In-Service Register
  • IMR: Interrupt Mask Register

中断虚拟化 - 内核端 - EwanHai - 博客园

8259A.pdf

Interrupt Evaluation / Recognition / Delivery

什么是 Evaluation of virtual interrupts？

One or more of the INTERRUPT REQUEST lines (IR7 –0) are raised high, setting the corresponding IRR bit(s). The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate.

我觉得可能包含进行一些 check，或者看看有没有在 IMR 里被置上需要被 mask 掉之类的，总之就是从 8 个引脚的电平转换成为一个发送到 CPU 的一个数字的过程。

什么是 Recognition of a virtual interrupt？

MSI Interrupt

MSIs are supported in PCI bus.

Traditionally, a device has an interrupt line (pin) which it asserts when it wants to signal an interrupt. This is an out-of-band control^ since it uses a dedicated path to send such control information. MSI replaces those dedicated interrupt lines with in-band signaling, by exchanging special messages that indicate interrupts through the main data path.

MSI allows the device to write interrupt-describing data to a special MMIO address (using memory write (MW) transaction^), and the chipset (Root Complex?) then delivers the corresponding interrupt to a processor.

MSI-X interrupts are standard Memory Writes

As an example, PCIe does not have separate interrupt pins at all.

The LAPIC must be enabled for the MSI/MSI-X to work.

MSIs are handled by writing the interrupt vector directly into the LAPIC of the processor/core that needs to service the interrupt. 无需经过传统的通过 I/O APIC 转发中断（device -> I/O APIC -> LAPIC）。

Message Signaled Interrupts - Wikipedia

How to enable MSI?

PCI devices are initialised to use pin-based interrupts. The device driver has to set up the device to use MSI or MSI-X.

To support MSI or MSI-X, the kernel must be built with the CONFIG_PCI_MSI option.

4. The MSI Driver Guide HOWTO — The Linux Kernel documentation

MSI Capability Structure / Registers

PCIE 6.0 SPEC: 7.7.1 MSI Capability Structures，注意，这里是 general 的定义，每个 arch 有自己的定义。

The MSI capability structure^ (in configuration space) contains

  • Message Control Register (MSI capability supported by the device)
  • Message Address Register（MSI Memory Transaction 写入的地址（要发给哪一个 LAPIC））
  • Message Data Register (MSI Memory Transaction 写入的数据（中断向量号）)

Message Address 和 Message Data 的格式由各个架构自己定义，对于 x86 架构，Message Address 就是位于 0xFEE00000 - 0xFEEFFFFF 的一块地址区域（和 LAPIC 的地址范围重合 SDM: 10.11.1 Message Address Register Format）。

When PCI device write to the MSI address, how does LAPIC be awared?

A single assigned MSI slot in the LAPIC corresponds to exactly one PCI-e device.

The LAPIC registers are memory mapped to an address that can be found in the MP/MADT tables.

The MSI will eventually go to Root Complex^. The root complex looks up the address in the TLP and determines that it is the address of a memory location (or CPU LAPIC).

linux device driver - How PCIE Root complex moves DMA transaction from PCIe endpoint to Host memory - Stack Overflow

drivers - Read address from MSI Capability Structure - Stack Overflow

Microsoft Word - 深入理解MSI,MSI-X中断和中断虚拟化-liujunming.docx

Advantage of using MSI

  • fewer pins makes for a simpler, cheaper, and more reliable connector.
  • MSI increases the number of interrupts that are possible.
  • slight performance advantage

Message Signaled Interrupts - Wikipedia

Out-of-band control

Passes control data on a separate connection from main data.

PCIe INTx interrupt

The legacy one compared to MSI.

PCI INTx interrupts are implemented using side-band signals.