A linear address is 48-bit canonical if bits 63:47 of the address are identical; it is 57-bit canonical if bits 63:56 are identical. (Clearly, any linear address that is 48-bit canonical is also 57-bit canonical.)

The canonicality enforcement implies that software would have to mask the metadata bits in a pointer (making it canonical) before using it as a linear address to access memory.

LAM allows software to use pointers with metadata without having to mask the metadata bits. With LAM enabled, the processor masks the metadata bits in a pointer before using it as a linear address to access memory.

LAM is supported only in 64-bit mode and applies only addresses used for data accesses.

The LAM width may be configured differently for user and supervisor pointers. LAM identifies pointer as a user pointer if bit 63 of the pointer is 0 and as a supervisor pointer if bit 63 of the pointer is 1.

Enumerate: CPUID.(EAX=07H, ECX=01H):EAX.LAM[bit 26]

Enable: CR3[62] (LAM_U48), CR3[61] (LAM_U57), and CR4[28] (LAM_SUP).

Processors that support LAM continue to require the addresses written to control registers or MSRs be 57-bit canonical if the processor supports 5-level paging or 48-bit canonical if it supports only 4-level paging; LAM masking is not performed on these writes. When the contents of such registers are used as pointers to access memory, the processor performs canonicality checking and masking based on paging mode and LAM mode configuration active at the time of access.

  • LAM_S48 (indicates 4 level paging): bit 47 and bit 63 are 1.
  • LAM_S57 (indicates 5 level paging): bit 56 and bit 43 are 1.
  • LAM_U48 + 4 level paging: bit 47 and bit 63 are 0.
  • LAM_U48 + 5 level paging: bit 47 and bit 63 are 0 (LAM wins).
  • LAM_U57 + 4 level paging: bit 47 - 56 are 0, bit 63 is 0.
  • LAM_U57 + 5 level paging: bit 56 and bit 63 are 0.

5 Level paging and LAM_U48

For user pointer, there is possibility that 5 level paging is used and LAM_U48 is also used. In this case, the effective usable linear address width is 48 (LAM win).

In this case, bit 47 is 0, bits 56:48 contains metadata. Because these bits should be translated by 5-level paging, so they are always 0 in any linear address derived from an user pointer.